Work you will do: Debug Verilog AMS/DMS models Run DMS simulations in Cadence or Synopsys co-simulation environmentAbility view schematics in VirtuosoGood Understanding of Real Number Modeling techniques and challengesUnderstanding of [...]
Work you will do: · Testbench development - System Verilog UVM and C tests· Integration/development of C tests/APIs and SW build flow· Integration/development of UVM mailboxes and HW/SW communication components· Test plan developme[...]
Responsibilities: Maintain software design environment Maintain and configure continuous integration, issue tracking, and configuration management tools Support the design community Advise and recommend branching and streaming strategi[...]
Join our team and what we'll accomplish together The Data Strategy & Enablement team is on a continuous journey towards helping TELUS become a world-class leader in data solutions, doing so by delivering data analytics capabilities built upon
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Job Description We Are:The Silicon Design group is a diverse team of world class silicon design, verification and validation experts. We have 100+ years of cumulative hands-on experience in architecture, logic design, verification, physical
Execute a project independently with global teams to achieve pre-defined goals in timeUnderstand logical design architecture and provide the analyzed data to architects for reviewImprove existing UVM test bench with advanced design[...]
Develop and maintain SoC and subsystems synthesizable RTL, design methodology and infrastructureCollaborate directly with IP Architecture, SoC Architecture and Design LeadsDebug and resolve issues with SoC Integration, SoC Design Verif[...]
Develop and maintain SoC and subsystems synthesizable RTL, design methodology and infrastructureDebug and resolve issues with SoC Integration, SoC Design Verification and post-silicon validation teamsWork with IP development teams and [...]