Technology Lead- Memory Layout
About the role
K&K Global Talent Solutions Inc is an International recruiting agency that has been providing technical resources in Canada region since 1993. This position is with one of our clients in Canada, who is actively hiring candidates to expand their teams.
Role: Technology Lead- Memory Layout Employment type: Full time Technology: DRC, LVS, ERC Location: Vancouver, BC (On-site)
Job Description- Candidate must be located within commuting distance of Vancouver BC, Canada or be willing to relocate to the area. This position may require travel in Canada. Bachelor’s degree or foreign equivalent required from an accredited institution. Will also consider three years of progressive experience in the specialty in lieu of every year of education. At least 4 years of Information Technology experience. Candidates authorized to work for any employer in the Canada without employer-based visa sponsorship are welcome to apply. Client is unable to provide immigration sponsorship for this role at this time.
Required Skills : Minimum Qualifications 5+ years of experience in Compiler/Custom Memory Layout design. Memory Leafcell layout library design from scratch including top level integration. Good knowledge on diAerent types of memory architectures. Good knowledge in optimized layout design for better performance. Sound knowledge & hands on experience in Finfet technology, layout design and DRC limitations. 3nm, 5 nm exposure required Proficient in physical verification flow & debug, like DRC, LVS, ERC,
Boundary conditions. Proficient in Cadence Virtuoso layout editor and Calibre physical verification flow
Note: Applicants for employment in Canada should possess work authorization which does not require sponsorship by the employer for a visa
About K&K Global Talent Solutions INC.
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Technology Lead- Memory Layout
About the role
K&K Global Talent Solutions Inc is an International recruiting agency that has been providing technical resources in Canada region since 1993. This position is with one of our clients in Canada, who is actively hiring candidates to expand their teams.
Role: Technology Lead- Memory Layout Employment type: Full time Technology: DRC, LVS, ERC Location: Vancouver, BC (On-site)
Job Description- Candidate must be located within commuting distance of Vancouver BC, Canada or be willing to relocate to the area. This position may require travel in Canada. Bachelor’s degree or foreign equivalent required from an accredited institution. Will also consider three years of progressive experience in the specialty in lieu of every year of education. At least 4 years of Information Technology experience. Candidates authorized to work for any employer in the Canada without employer-based visa sponsorship are welcome to apply. Client is unable to provide immigration sponsorship for this role at this time.
Required Skills : Minimum Qualifications 5+ years of experience in Compiler/Custom Memory Layout design. Memory Leafcell layout library design from scratch including top level integration. Good knowledge on diAerent types of memory architectures. Good knowledge in optimized layout design for better performance. Sound knowledge & hands on experience in Finfet technology, layout design and DRC limitations. 3nm, 5 nm exposure required Proficient in physical verification flow & debug, like DRC, LVS, ERC,
Boundary conditions. Proficient in Cadence Virtuoso layout editor and Calibre physical verification flow
Note: Applicants for employment in Canada should possess work authorization which does not require sponsorship by the employer for a visa