About the role
Must: System Verilog & UVM
Description
DV engineer with 3+-13 yrs of exp. Verification of display IP used in graphics card IP/SS and end to end testing for these blocks. Exp in DV flow including SV, UVM
Similar Jobs
About the role
Must: System Verilog & UVM
Description
DV engineer with 3+-13 yrs of exp. Verification of display IP used in graphics card IP/SS and end to end testing for these blocks. Exp in DV flow including SV, UVM